The present invention relates to a selective metallization process, particularly to the manufacture of printed circuit boards and, more particularly, to an improved manufacturing sequence for producing printed circuits having thru-holes requiring metallization. The invention also relates to a composition for use in this manufacturing sequence.
Selective metallization processes, whereby metal is provided on a substrate in a predetermined aesthetic and/or functional pattern, are well known and have particular commercial application in the manufacture of printed circuit boards.
In the manufacture of printed circuit boards, it is now commonplace to produce printed circuitry on both sides of a planar rigid or flexible insulating substrate. Of increased importance is the manufacture of multilayer printed circuits. In these products, the board consists of parallel, planar, alternating innerlayers of insulating substrate material and conductive metal. The exposed outer sides of the laminated structure are provided with circuit patterns as with double-sided boards, and the metal innerlayers may themselves contain circuit patterns.
In double-sided and multilayer printed circuit boards, it is necessary to provide conductive interconnection between or among the various layers or sides of the board containing conductive circuitry. This is commonly achieved by providing metallized, conductive thru-holes in the board communicating with the sides and layers requiring electrical interconnection. Typically, thru-holes are drilled or punched through the board structure at desired locations. The thus exposed hole surfaces, consisting partly or entirely of insulating material, are then metallized, generally by utilization of electroless metal depositing techniques.
In terms of providing the desired circuit pattern on the board, the art has developed a variety of manufacturing sequences, many of which fall into the broad categories of "subtractive" or "additive" techniques. Common to subtractive processes is the need to etch away (or subtract) metal to expose substrate surface in areas where no circuitry is desired. Accordingly, some disadvantages associated with subtractive processes include the necessity of using relatively large quantities of etching solutions, possible undesired undercutting of metal in areas where metal is supposed to remain, and waste of base metal (or need for processes to reclaim base metal).
Additive processes, on the other hand, begin with exposed substrate surfaces and build up thereon metallization in desired areas, the desired areas being those not masked by a previously-applied pattern of plating resist material (e.g., photoresist in negative pattern). While avoiding the problems associated with the etching required in subtractive processes, additive processes are not without their own inherent difficulties in terms of the choice of resist materials and the ability to build up to the full metallization desired by electroless methods.
In one additive technique known in the art, the insulating substrate surfaces are first sensitized and activated to form a blanket catalyzed layer thereon. Next, the appropriate resist pattern is formed over the catalyzed layer so as to leave exposed the areas where metallization is desired. Thereafter, the substrate is treated in an electroless metal depositing solution to effect metallization only of the catalyzed and exposed desired areas. In this process, however, it is necessary after removal of the resist to etch away the catalytic layer which was under the resist so as to prevent excessively low surface resistivity between metallized areas on the substrate due to the catalytic layer.
In another proposed technique, a negative pattern of resist is first applied to the substrate surfaces. The entire surface (including the resist surfaces) is then sensitized and activated, followed by treatment of the entire surface with an electroless metal depositing solution, resulting in deposit of metal on all surfaces. The resist is then stripped from the substrate surface, carrying along with it the metal deposited thereon, and thus leaving behind the build up metallized pattern. In this process, however, the deposition of metal over the resist is quite substantial and leads to difficulties in cleanly stripping the resist, often resulting in the remaining metallized areas adjacent the resist (e.g. conductors) having ragged edges or slivers, correspondingly poor fine line resolution or definition, and risk of shorting.
U.S. Pat. No. 4,388,351 to Sawyer sought to improve upon the foregoing by depositing over all surfaces (including resist surfaces) only a thin flash layer of electroless metal, followed by stripping of the resist and electroless build up to full desired metallization on the patterned flash surfaces remaining. The Sawyer technique, applicable to use with photoresists of the type which require hydrocarbon solvents for development and stripping, was extended by Dorey, II, et al. in U.S. Pat. No. 4,574,031 so as to have applicability to photoresists of the type which can be developed and stipped in aqueous alkaline solutions.
In processes of the Sawyer and Dorey, II, et al. type, the degree or extent of flash plating must be controlled within relatively narrow limits. On the one hand, sufficient thickness is required in order for the flash plate to serve its intended purpose as a defined base upon which further metallization can be built up in the required pattern after resist removal. However, if the flash deposit is too thick, stripping of the resist is quite difficult and may lead to the existence of ragged edges or metal slivers or whiskers in flash plated areas adjacent to where the resist existed. In practice, it has proven to be quite difficult to strike a proper balance within the narrow confines of the process. Particular difficulty also is found with respect to thru-hole coverage. In those cases where the flash plate is sufficiently thin so as not to interfere with resist removal, thru-hole coverage by metal is poor; but when the process is arranged so as to provide better thru-hole coverage, the increased thickness of the layer plated on the resist interferes with resist removal.